Intel® Agilex™ Hard Processor System Technical Reference Manual

ID 683567
Date 11/11/2022
Public

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3.5.13. Generic Interrupt Controller

The ARM® Generic Interrupt Controller (GIC-400) resides within the system complex outside of the Cortex® -A53 processor. The GIC is shared by all of the Cortex® -A53 CPUs.

The GIC has software-configurable settings to detect, manage and distribute interrupts in the SoC.

  • Interrupts are enabled or disabled and prioritized through control registers.
  • Interrupts can be prioritized and signaled to different processors.
  • You can configure interrupts as secure or non-secure by assigning them to group 0 or group1, respectively.
  • Virtualization extensions within the GIC allow you to manage virtualized interrupts.
The GIC provides 205 shared interrupt sources, including dedicated peripherals and IP implemented in the FPGA fabric. Each CPU also has six external private peripheral interrupts and one internal private peripheral interrupt. All four CPUs share 16 banked software-generated interrupts (SGIs).
Note: Legacy IRQs are not supported by the GIC.

The GIC detects private peripheral interrupts (PPIs) and shared peripheral interrupts (SPIs) from interrupt signals. Software-generated interrupts are detected through the register interface. Each CPU generates a signal for every private peripheral interrupt ID (PPI ID). There is only one input signal for each SPI interrupt ID shared among the four CPUs. The GIC supports virtual interrupts as well.

The GIC notifies each CPU of an interrupt or virtual interrupt through output signals sent to the Cortex® -A53 MPCore™ .

The configuration and control for the GIC is memory-mapped and accessed through the cache coherency unit (CCU).