Intel® Agilex™ Hard Processor System Technical Reference Manual

ID 683567
Date 11/11/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

6.1.1. Masters and Slaves Connectivity Matrix

The following table shows the connectivity of all the master and slave interfaces in the system interconnect.
Table 49.  Master-to-Slave Connectivity
Slaves Masters
DAP CCU Master 2 DMAC 3 EMAC 0/1/2 Peripheral Master 4
CCU Slaves 5  
TCU      
L4 Main Bus Slaves    
L4 MP Bus Slaves      
L4 AHB Bus Slaves      
L4 SP Bus Slaves    
L4 SYS Bus Slaves    
Secure/Non-Secure Timestamp System Counters    
L4 ECC Bus Slaves      
L4 SHR Bus (Clock, Reset and System Manager)      
DAP     6
STM      
Lightweight HPS-to-FPGA Bridge
HPS-to-FPGA Bridge
Service Network      
HPS-to-SDM – Peripheral Access (QSPI, SD/MMC)    
HPS-to-SDM – Mailbox Access      
2 CCU Master Agent: Cortex-A53 MPCore, FPGA-to SoC, HPS peripheral masters, TCU
3 Direct Memory Access Controller
4 Peripheral Master TBU, including:
  • TBU for EMAC 0/1/2
  • TBU for USB 0/1, NAND, SD/MMC, and ETR
  • TBU for DMAC
5 CCU Slaves: MPFE, on-chip RAM, GIC, HPS peripheral slaves
6 ETR access only.