Intel® Agilex™ Hard Processor System Technical Reference Manual

ID 683567
Date 11/11/2022
Public

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16.5.10.2. Card Read Threshold Programming Sequence

Most cards, such as SDHC or SDXC, support block sizes that are either specified in the card or are fixed to 512 bytes. For SDIO, MMC, and standard capacity SD cards that support partial block read (READ_BL_PARTIAL set to 1 in the CSD register of the card device), the block size is variable and can be chosen by the application.

To use the card read threshold feature effectively and to guarantee that the card clock does not stop because of a FIFO Full condition in the middle of a block of data being read from the card, follow these steps:

  1. Choose a block size that is a multiple of four bytes.
  2. Enable card read threshold feature. The card read threshold can be enabled only if the block size for the given transfer is less than or equal to the total depth of the FIFO buffer:

    (block size / 4) ≤ 1024

  3. Choose the card read threshold value:
    • If (block size / 4) ≥ 512, choose cardrdthreshold such that:
      • cardrdthreshold ≤ (block size / 4) in bytes
    • If (block size / 4) < 512, choose cardrdthreshold such that:
      • cardrdthreshold = (block size / 4) in bytes
  4. Set the dw_dma_multiple_transaction_size field in the fifoth register to the number of transfers that make up a DMA transaction. For example, size = 1 means 4 bytes are moved. The possible values for the size are 1, 4, 8, 16, 32, 64, 128, and 256 transfers. Select the size so that the value (block size / 4) is evenly divided by the size.
  5. Set the rx_wmark field in the fifoth register to the size – 1.

For example, if your block size is 512 bytes, legal values of dw_dma_multiple_transaction_size and rx_wmark are listed in the following table.

Table 163.  Legal Values of dw_dma_multiple_transaction_size and rx_wmark for Block Size = 512
Block Size dw_dma_multiple_transaction_size rx_wmark

512

1

0

512

4

3

512

8

7

512

16

15

512

32

31

512

64

63

512

128

127