Intel® Agilex™ Hard Processor System Technical Reference Manual

ID 683567
Date 11/11/2022
Public

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3.6.3. Enabling and Disabling Cache

You can enable the instruction and data caches in the System Control Register (SCTLR).

If you disable the instruction cache, all instruction fetches are treated as non-cacheable. Only instruction cache maintenance operations continue to be maintained when the instruction cache is disabled.

You cannot enable and disable the L1 and L2 data caches separately because they are controlled by the same enable. If you disable the data cache, loads and stores are treated as non-cacheable. Only cache maintenance operations continue to be maintained in the data caches.