Intel® Agilex™ Hard Processor System Technical Reference Manual

ID 683567
Date 11/11/2022
Public

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16.4.3.4.3. Data Receive

  • Data timeout—during a read‑data transfer, if the data start bit is not received before the number of clock cycles specified in the timeout register, the data path does the following action:
    • Signals a data‑timeout error to the BIU
    • Terminates further data transfer
    • Signals data transfer done to BIU
  • Data SBE—during a 4‑bit or 8‑bit read‑data transfer, if the all‑bit data line does not have a start bit, the data path signals a data SBE to the BIU and waits for a data timeout, after which it signals that the data transfer is done.
  • Data CRC error—during a read‑data‑block transfer, if the CRC‑16 received does not match with the internally generated CRC‑16, the data path signals a data CRC error to the BIU and continues with the data transfer.
  • Data EBE—during a read‑data transfer, if the end bit of the received data is not 1, the data path signals an EBE to the BIU, terminates further data transfer, and signals to the BIU that the data transfer is done.
  • Data starvation due to FIFO buffer full—during a read data transmission and when the FIFO buffer becomes full, the card clock stops. If the FIFO buffer remains full for a data-timeout number of clock cycles, the data path signals a data starvation error to the BIU, by setting the data starvation host timeout bit (hto) in rintsts register to 1, and the data path continues to wait for the FIFO buffer to empty.