Intel® Agilex™ Hard Processor System Technical Reference Manual

ID 683567
Date 11/11/2022
Public

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16.5.10.1. Recommended Usage Guidelines for Card Read Threshold

  1. The cardthrctl register must be set before setting the cmd register for a data read command.
  2. The cardthrctl register must not be set while a data transfer command is in progress.
  3. The cardrdthreshold field of the cardthrctl register must be set to at the least the block size of a single or multiblock transfer. A cardrdthreshold field setting greater than or equal to the block size of the read transfer ensures that the card clock does not stop in the middle of a block of data.
  4. If the round trip delay is greater than half of the card clock period, card read threshold must be enabled and the card threshold must be set as per guideline 3 to guarantee that the card clock does not stop in the middle of a block of data.
  5. If the cardrdthreshold field is set to less than the block size of the transfer, the host must ensure that the receive FIFO buffer never overflows during the read transfer. Overflow can cause the card clock from the controller to stop. The controller is not able to guarantee that the card clock does not stop during a read transfer.
Note: If the cardrdthreshold field of the cardthrctl register, and the rx_wmark and dw_dma_multiple_transaction_size fields of the fifoth register are set incorrectly, the card clock might stop indefinitely, with no interrupts generated by the controller.