Intel® Agilex™ Hard Processor System Technical Reference Manual

ID 683567
Date 11/11/2022
Public

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16.4.3.1.9. I/O transmission delay (NACIO Timeout)

The host software maintains the timeout mechanism for handling the I/O transmission delay (NACIO cycles) time‑outs while reading from the CE‑ATA card device. The controller neither maintains any timeout mechanism nor indicates that NACIO cycles are elapsed while waiting for the start bit of a data token. The I/O transmission delay is applicable for read transfers using the RW_REG and RW_BLK commands; the RW_REG and RW_BLK commands used in this document refer to the RW_MULTIPLE_REGISTER and RW_MULTIPLE_BLOCK MMC commands defined by the CE‑ATA specification.
Note: After the NACIO timeout, the application must abort the command by sending the CCSD and STOP commands, or the STOP command. The Data Read Timeout (DRTO) interrupt might be set to 1 while a STOP_TRANSMISSION command is transmitted out of the controller, in which case the data read timeout boot data start bit (bds) and the dto bit in the rintsts register are set to 1.