Intel® Agilex™ Hard Processor System Technical Reference Manual

ID 683567
Date 11/11/2022
Public

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15.5.2.1.2. Multi-Plane Erase

For multi‑plane erases, the number_of_planes register in the config group holds the number of planes in the flash device, and the block address specified must be aligned to the number of planes in the device. The NAND flash controller consecutively erases each block of the memory, up to the number of planes available. Issue this command as follows:
  1. Write to the command register, setting the CMD_MAP field to 2 and the BLK_ADDR field to the desired erase block.
  2. Write 0x01 to the Data register.

For multi‑plane erase, the register multiplane_operation in the config group must be set.

After the device completes erase operation on all planes, the NAND flash controller generates an erase_comp interrupt. If the erase operation fails on any of the blocks in a multi‑plane erase command, an erase_fail interrupt is issued. The failing block's address is updated in the err_block_addr0 register in the status group.