Intel® Agilex™ Hard Processor System Technical Reference Manual

ID 683567
Date 11/11/2022
Public

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14.2. Intel® Agilex™ HPS I/O System Integration

The HPS I/O block consists of the following sub-blocks:

  • Dedicated pin multiplexers (MUXes) – MUXes for the dedicated I/O bank
  • FPGA access pin multiplexers – MUXes for HPS peripheral connections to the FPGA fabric
  • Register slave interface – Provides access to control registers, which allow the bootloader to initialize I/O pins and HPS peripheral interfaces at system startup