Intel® Agilex™ Hard Processor System Technical Reference Manual

ID 683567
Date 11/11/2022
Public

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12.3.1.3. EMAC

You can program the emac_global register to select either emac_ptp_clk from the Clock Manager or f2h_ptp_ref_clk from the FPGA fabric as the source of the IEEE 1588 reference clock for each EMAC.

You can program the system manager's emac* register to control the EMAC's ARCACHE and AWCACHE signals. These bits define the cache attributes for the master transactions of the DMA engine in the EMAC controllers.

Note:

Register bits must be accessed only when the master interface is guaranteed to be in an inactive state.

The phy_intf_sel bit is programmed to select between a GMII (MII), RGMII or RMII PHY interface when the peripheral is released from reset. The ptp_ref_sel bit in the emac* registers selects if the timestamp reference is internally or externally generated. The ptp_ref_sel bit must be set to the correct value before the EMAC core is pulled out of reset.

Note: EMAC0 must be set to internal timestamp.