Intel® Agilex™ Hard Processor System Technical Reference Manual

ID 683567
Date 11/11/2022
Public

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Document Table of Contents

2. Introduction to the Hard Processor System

The Intel® Agilex™ system-on-a-chip (SoC) is composed of two distinct portions: a 64-bit quad core ARM® Cortex*-A53 MPCore™ hard processor system (HPS) and an FPGA. The HPS architecture integrates a wide set of peripherals that reduce board size and increase performance within a system.

The HPS communicates outside of the SoC through the following types of interfaces:
  • Dedicated I/O interfaces
  • FPGA fabric interfaces
  • FPGA secure device manager (SDM) interfaces
Key modules in the HPS include:
  • Quad core ARM® Cortex*-A53 MPCore™ processor
  • Level 3 (L3) interconnect
  • Cache Coherency Unit (CCU)
  • System Memory Management Unit (SMMU)
  • Multi-port front end (MPFE) subsystem, consisting of the hard memory controller adaptor and interface to the CCU interconnect
  • DMA Controller
  • On-chip RAM
  • Debug components
  • PLLs
  • Flash memory controllers
  • Support peripherals
  • Interface peripherals

The HPS incorporates third-party intellectual property (IP) from several vendors.

The FPGA portion of the device contains:
  • FPGA fabric
  • PLLs
  • User I/O
  • Hard memory controllers
  • Secure Device Manager (SDM)

The HPS and FPGA portions of the device each have their own pins. The HPS has dedicated I/O pins. You can also route most of the HPS peripherals into the FPGA fabric to use the FPGA I/O. You can configure pin placement assignments when you instantiate the HPS component in Intel® Platform Designer System Integration Tool.

You can boot the SoC from a power-on reset in one of two ways:
  • FPGA configures first and then optionally boots the HPS (also called FPGA Configuration First).
  • HPS boots first and then configures the FPGA (called HPS Boot First).

For more information, refer to the "Boot and Configuration" appendix.