Intel® Agilex™ Hard Processor System Technical Reference Manual

ID 683567
Date 11/11/2022
Public

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8.3.1. Error Checking and Correction

There is a dual port SRAM local memory buffer that provides ECC capability and is 64 by 512 bits, providing 4096 bytes of memory. One of the ports is always used for writes, and the other is always used for reads. The ECC block is integrated around the SRAM local memory buffer and provides the following features:

  • Output to notify the system manager when single-bit correctable errors are detected and corrected
  • Output to notify the system manager when double-bit uncorrectable errors are detected
  • Provision for the injection of single-bit and double-bit errors for test purposes

The system manager provides registers to set or mask single-bit or double-bit ECC error interrupts.