Intel® Agilex™ Hard Processor System Technical Reference Manual

ID 683567
Date 11/11/2022
Public

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6.1.3. Rate Adapter

The system interconnect implements a rate adapter to buffer data packets carrying requests from L3 master peripherals to the L3 interconnect. It transfers low-bandwidth channels data to high-bandwidth channels.

The rate adapter module, noc_mpu_m0_L4_MP_rate_ad_main_RateAdapter, is positioned between datapaths clocked by l3_main_free_clk and datapaths clocked by the divided-down clocks l4_mp_clk, l4_sp_clk, and l4_sys_clk. At these bandwidth discontinuities, the rate adapter ensures efficient use of interconnect data pathways. You can configure the rate adapter using the L4_MP_rate_ad_main_RateAdapter_Rate register.