Intel® Agilex™ Hard Processor System Technical Reference Manual

ID 683567
Date 11/11/2022
Public

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20.3. I2C Controller Signal Description

All instances of the I2C controller connect to external pins through pin multiplexers. Pin multiplexing allows all instances to function simultaneously and independently. The pins must be connected to a pull-up resistors and the I2C bus capacitance cannot exceed 400 pF.

There are five instances of the I2C which can be routed to the HPS I/O pins. Three of these I2C modules can be used for PHY management by the three Ethernet Media Access Controllers within the HPS.

Table 202.   I2C Controller Interface Signals (Routed to HPS I/O)
Signal Name Width Direction Description Default Value for Inputs Recommended Tie-off
I2C<1:0>_SCL 1 Bidirectional Serial clock --- Pull-up
I2C<1:0>_SDA 1 Bidirectional Serial data --- Pull-up
Table 203.   I2C Controller Interface Signals (Routed to FPGA I/O)
Signal Name Width Direction Description Default Value for Inputs Recommended Tie-off
i2c<1:0>_scl_i 1 Input Incoming I2C clock source. This is the input SCL signal 1'b1 Pull-up
i2c<1:0>_scl_oe 1 Output Outgoing I2C clock enable. Output SCL signal. This signal is logically inverted and is synchronous to the HPS peripheral clock --- Pull-up
i2c<1:0>_sda_i 1 Input Incoming I2C data. This is the input SDA signal 1'b1 Pull-up
i2c<1:0>_sda_oe 1 Output Outgoing I2C data enable. Output SDA signal. This signal is logically inverted and is synchronous to the HPS peripheral clock. --- Pull-up
s2f_i2c<1:0>_irq 1 Output Interrupt --- ---
Figure 100. I2C Interface in FPGA Fabric


The figure above shows the typical connection on the I2C interface in FPGA fabric with alt_iobuff.

For both I2C clock and data, external IO pins are open drain connection. When output enables i2c<#>_sda_oe and i2c<#>_clk_clk are asserted, external signal is driven to ground.