Intel® Agilex™ Hard Processor System Technical Reference Manual

ID 683567
Date 11/11/2022
Public

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12.3.1.1. DMA Controller

The security state of the DMA controller is controlled by the manager thread security (mgr_ns) and interrupt security (irq_ns) bits of the DMA register.

The ns bits of the dma_periph register determine if a peripheral request interface is secure or non-secure.

Note: The ns bits of the dma_periph register must be configured before the DMA is released from global reset.