Intel® Agilex™ Hard Processor System Technical Reference Manual

ID 683567
Date 11/11/2022
Public

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15.4.4. Local Memory Buffer

The NAND flash controller has three FIFO memories implemented using dual-ported SRAM.
  • Write FIFO—The read data from the host memory resides in the Write FIFO before being flushed to the memory.
  • Read FIFO—The data from the device is read and stored in the FIFO before being forwarded to the host memory.
  • ECC FIFO—This buffer holds data for applying the ECC correction while the logic computes error locations and mask.

Each of these memories is protected by ECC, and by interrupts for single and double-bit errors. The ECC block is integrated around a memory wrapper. It provides outputs to notify the system manager when single-bit correctable errors are detected (and corrected); and when double-bit uncorrectable errors are detected. The ECC logic also allows injection of single- and double-bit errors for test purposes. It must be initialized to enable the ECC function.

For more information about ECC, refer to the Error Checking and Correction Controller chapter.