Intel® Agilex™ Hard Processor System Technical Reference Manual

ID 683567
Date 11/11/2022
Public

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16.5.10. Card Read Threshold

When an application needs to perform a single or multiple block read command, the application must set the cardthrctl register with the appropriate card read threshold size in the card read threshold field (cardrdthreshold) and set the cardrdthren bit to 1. This additional information specified in the controller ensures that the controller sends a read command only if there is space equal to the card read threshold available in the RX FIFO buffer. This in turn ensures that the card clock is not stopped in the middle a block of data being transmitted from the card. Set the card read threshold to the block size of the transfer to guarantee there is a minimum of one block size of space in the RX FIFO buffer before the controller enables the card clock.

The card read threshold is required when the round trip delay is greater than half of sdmmc_clk_divided.

Table 162.  Card Read Threshold Guidelines
Bus Speed Modes Round Trip Delay (Delay_R) 38 Is Stopping of Card Clock Allowed? Card Read Threshold Required?

SDR25

Delay_R > 0.5 * (sdmmc_clk/4)

Delay_R < 0.5 * (sdmmc_clk/4)

No

Yes

Yes

No

SDR12

Delay_R > 0.5 * (sdmmc_clk/4)

Delay_R < 0.5 * (sdmmc_clk/4)

No

Yes

Yes

No

38

Delay_R = Delay_O + tODLY + Delay_I

Where:

Delay_O = sdmmc_clk to sdmmc_cclk_out delay (including I/O pin delay)

Delay_I = Input I/O pin delay + routing delay to the input register

tODLY = sdmmc_cclk_out to card output delay (varies across card manufactures and speed modes)