Intel® Agilex™ Hard Processor System Technical Reference Manual

ID 683567
Date 11/11/2022
Public

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16.4.3.2.1. Data Transmit

The data transmit state machine starts data transmission two clock cycles after a response for the data write command is received. This occurs even if the command path detects a response error or response CRC error. If a response is not received from the card because of a response timeout, data is not transmitted. Depending upon the value of the transfer mode bit (transfer_mode) in the cmd register, the data transmit state machine puts data on the card data bus in a stream or in blocks.
Figure 48. Data Transmit State Machine

Stream Data Transmit

If the transfer_mode bit in the cmd register is set to 1, the transfer is a stream‑write data transfer. The data path reads data from the FIFO buffer from the BIU and transmits in a stream to the card data bus. If the FIFO buffer becomes empty, the card clock is stopped and restarted once data is available in the FIFO buffer.

If the bytcnt register is reset to 0, the transfer is an open‑ended stream‑write data transfer. During this data transfer, the data path continuously transmits data in a stream until the host software issues an SD/SDIO STOP command. A stream data transfer is terminated when the end bit of the STOP command and end bit of the data match over two clock cycles.

If the bytcnt register is written with a nonzero value and the send_auto_stop bit in the cmd register is set to 1, the STOP command is internally generated and loaded in the command path when the end bit of the STOP command occurs after the last byte of the stream write transfer matches. This data transfer can also terminate if the host issues a STOP command before all the data bytes are transferred to the card bus.

Single Block Data

If the transfer_mode bit in the cmd register is set to 0 and the bytcnt register value is equal to the value of the block_size register, a single‑block write‑data transfer occurs. The data transmit state machine sends data in a single block, where the number of bytes equals the block size, including the internally‑generated 16‑term CRC (CRC‑16).

If the ctype register is set for a 1‑bit, 4‑bit, or 8‑bit data transfer, the data is transmitted on 1, 4, or 8 data lines, respectively, and CRC‑16 is separately generated and transmitted for 1, 4, or 8 data lines, respectively.

After a single data block is transmitted, the data transmit state machine receives the CRC status from the card and signals a data transfer to the BIU. This happens when the dto bit in the rintsts register is set to 1.

If a negative CRC status is received from the card, the data path signals a data CRC error to the BIU by setting the dcrc bit in the rintsts register.

Additionally, if the start bit of the CRC status is not received by two clock cycles after the end of the data block, a CRC status start‑bit error (SBE) is signaled to the BIU by setting the sbe bit in the rintsts register.

Multiple Block Data

A multiple‑block write‑data transfer occurs if the transfer_mode bit in the cmd register is set to 0 and the value in the bytcnt register is not equal to the value of the block_size register. The data transmit state machine sends data in blocks, where the number of bytes in a block equals the block size, including the internally‑generated CRC‑16 value.

If the ctype register is set to 1‑bit, 4‑bit, or 8‑bit data transfer, the data is transmitted on 1-, 4-, or 8-data lines, respectively, and CRC‑16 is separately generated and transmitted on 1-, 4-, or 8-data lines, respectively.

After one data block is transmitted, the data transmit state machine receives the CRC status from the card. If the remaining byte count becomes 0, the data path signals to the BIU that the data transfer is done. This happens when the dto bit in the rintsts register is set to 1.

If the remaining data bytes are greater than zero, the data path state machine starts to transmit another data block.

If a negative CRC status is received from the card, the data path signals a data CRC error to the BIU by setting the dcrc bit in the rintsts register, and continues further data transmission until all the bytes are transmitted.

If the CRC status start bit is not received by two clock cycles after the end of a data block, a CRC status SBE is signaled to the BIU by setting the ebe bit in the rintsts register and further data transfer is terminated.

If the send_auto_stop bit is set to 1 in the cmd register, the SD/SDIO STOP command is internally generated during the transfer of the last data block, where no extra bytes are transferred to the card. The end bit of the STOP command might not exactly match the end bit of the CRC status in the last data block.

If the block size is less than 4, 16, or 32 for card data widths of 1 bit, 4 bits, or 8 bits, respectively, the data transmit state machine terminates the data transfer when all the data is transferred, at which time the internally-generated STOP command is loaded in the command path.

If the bytcnt is zero (the block size must be greater than zero) the transfer is an open‑ended block transfer. The data transmit state machine for this type of data transfer continues the block‑write data transfer until the host software issues an SD/SDIO STOP or STOP_TRANSMISSION (CMD12) command.