Intel® Agilex™ Hard Processor System Technical Reference Manual

ID 683567
Date 11/11/2022
Public

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7.3.4.1. FPGA-to-SDRAM direct ( AXI* 4)

  • AxUSER[7:0] = 0xE0
  • All operations bypass the CCU and are non-coherent, therefore AxDOMAIN[1:0] must be ‘b00 (Non-shareable).
  • For all burst transactions, AxBURST must be either ‘b01 (INCR) or ‘b10 (WRAP).