Intel® Agilex™ Hard Processor System Technical Reference Manual

ID 683567
Date 11/11/2022
Public

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17.4.1.1. HPS-to-PHY Interface Diagrams

Each EMAC module in the HPS supports one PHY interface. If you are using the HPS pins for interfacing to a PHY, the following diagrams show the interface options available depending on what PHY you choose.
Figure 64. HPS EMAC to RGMII PHY Interface

Figure 65. HPS EMAC to RMII PHY with HPS-Sourced Reference Clock
Figure 66. HPS EMAC to RMII PHY with PHY-Sourced Reference Clock