Intel® Agilex™ Hard Processor System Technical Reference Manual

ID 683567
Date 11/11/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

16.4.2.5.2. Internal DMA Controller Descriptor Address

The descriptor address must be aligned to the 32‑bit bus. Each descriptor contains 16 bytes of control and status information.

Table 129.  Descriptor Format
Name Off- set 31 30 29:27 26 25:14 13 12:7 6 5 4 3 2 1 0
DES0 0 OWN CES ER CH FS LD DIC
DES1 4 BS2 BS1
DES2 8 BAP1
DES3 12 BAP2 or Next Descriptor Address