Intel® Agilex™ Hard Processor System Technical Reference Manual

ID 683567
Date 11/11/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

10.4.9. ECC Controller Reset

To access a peripheral's RAM and ECC configuration registers, both the peripheral and the ECC register interface must be out of reset.
  • Bring the peripheral out of reset by clearing the peripheral's corresponding reset bit in the per0modrst register of the Reset Manager.
  • Bring the peripheral's ECC register port out of reset by clearing the *ocp bit in the per0modrst register of the Reset Manager.

A cold or warm reset does not change the contents in the ECC RAM. These resets only clear the state associated with the bus slave.