Intel® Agilex™ Hard Processor System Technical Reference Manual

ID 683567
Date 11/11/2022
Public

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16.5.7.1. Internal DMA Controller Initialization

To initialize the internal DMA controller, perform the following steps:
  1. Set the required bmod register bits:
    • If the internal DMA controller enable bit (de) of the bmod register is set to 0 during the middle of a DMA transfer, the change has no effect. Disabling only takes effect for a new data transfer command.
    • Issuing a software reset immediately terminates the transfer. Prior to issuing a software reset, Intel recommends the host reset the DMA interface by setting the dma_reset bit of the ctrl register to 1.
    • The pbl field of the bmod register is read‑only and a direct reflection of the contents of the DMA multiple transaction size field (dw_dma_multiple_transaction_size) in the fifoth register.
    • The fb bit of the bmod register has to be set appropriately for system performance.
  2. Write to the idinten register to mask unnecessary interrupt causes according to the following guidelines:
    • When a Descriptor Unavailable interrupt is asserted, the software needs to form the descriptor, appropriately set its own bit, and then write to the poll demand register (pldmnd) for the internal DMA controller to re‑fetch the descriptor.
    • It is always appropriate for the software to enable abnormal interrupts because any errors related to the transfer are reported to the software.
  3. Populate either a transmit or receive descriptor list in memory. Then write the base address of the first descriptor in the list to the internal DMA controller’s descriptor list base address register (dbaddr). The DMA controller then proceeds to load the descriptor list from memory. Internal DMA Controller Transmission Sequences and Internal DMA Controller Reception Sequences describe this step in detail.