Intel® Agilex™ Hard Processor System Technical Reference Manual

ID 683567
Date 11/11/2022
Public

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8.1. Features of the DMA Controller

The HPS provides one DMAC to handle the data transfer between memory-mapped peripherals and memories, off-loading this work from the MPU System Complex. The DMAC has the following features:
  • A small instruction set that provides a flexible method of specifying the DMA operations. This architecture provides greater flexibility than the fixed capabilities of a Linked-List Item (LLI) based DMA controller
  • Software programmable with dedicated register field
  • Supports multiple transfer types:
    • Memory-to-memory
    • Memory-to-peripheral
    • Peripheral-to-memory
    • Scatter-gather
  • Supports eight DMA channels
  • Supports eight outstanding AXI read and eight outstanding AXI write transactions
  • Enables software to schedule up to 16 outstanding read and 16 outstanding write instructions
  • Supports nine interrupt lines into the MPU System Complex:
    • One for DMA thread abort
    • Eight for external events
  • Supports up to 32 peripheral request interfaces9:
    • Eight for FPGA10:
      • FPGA_0 - FPGA_5
      • FPGA_6 is multiplexed with I2C_EMAC2_TX
      • FPGA_7 is multiplexed with I2C_EMAC2_RX
    • Ten for I2C:
      • I2C_EMAC2 TX is multiplexed with FPGA_6
      • I2C_EMAC2 RX is multiplexed with FPGA_7
      • I2C0 (TX and RX) - I2C1 (TX and RX)
      • I2C_EMAC0 (TX and RX) - I2C_EMAC1 (TX and RX)
    • Eight for SPI
    • One for System Trace Macrocell (STM)
    • Four for UART
The following peripheral interface protocols are supported:
  • Synopsys® protocol, which is used by the following peripheral interfaces:
    • Serial peripheral interface (SPI)
    • Universal asynchronous receiver transmitter (UART)
    • Inter-integrated circuit (I2C)
    • FPGA interface
  • ARM® protocol, which is used by the STM peripherals.
    • System trace macrocell (STM) peripherals11
The DMA controller provides:
  • Linux drivers for DMA transfers
  • An ARM® Advanced Microcontroller Bus Architecture ( AMBA* ) Advanced eXtensible Interface ( AXI* ) master interface unit
  • A multi-FIFO (MFIFO) data buffer that it uses to store data that it reads, or writes, during a DMA transfer

Dual slave interfaces enable the operation of the DMA controller to be partitioned into a secure and non-secure state. The network interconnect must be configured to ensure that only secure transactions can access the secure interface. The slave interfaces provide access to status registers and are used to directly issue and execute instructions in the DMA controller.

9 Three of the interfaces are Reserved.
10 The HPS requires a total of 33 peripheral request interfaces, while the DMAC supports a maximum of 32 interfaces; therefore, FPGA_6 and FPGA_7 are controlled by the system manager software control registers.
11 Supports the same ARM® protocol and does not need an adapter.