Intel® Agilex™ Hard Processor System Technical Reference Manual

ID 683567
Date 11/11/2022
Public

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6.2. System Interconnect Clocks

The clock manager drives the system interconnect clocks. The system interconnect's clocks are part of the Interconnect clock group, which is hardware-sequenced. All clocks within a domain are synchronous with each other.

The main domain is largest synchronous domain in the interconnect, containing most of the datapath. The main domain generally consists of a single free-running clock and divided clocks with enables. Resets in the main domain depend on clock groups. Each clock group in the table below uses a single reset. Paths crossing different groups also cross asynchronous reset domains.
Table 60.  Clocks in the Main Clock Domain
Group Clock Clock Divider Reset Usage
main l3_main_free_clk - l3_rst_n clocks most of the interconnect datapath
l4_main_clk 1 DMAC and SPI
l4_mp_clk 2 EMAC, SDMMC, NAND, USB, ECC
l4_sp_clk 4 L4_SP bus
l4_sys_clk 4 L4_SYS bus
syscfg l4_sys_clk 4 syscfg_rst_n L4_SHR and L4_SEC buses
dbg cs_at_clk 1 dbg_rst_n  CoreSight
cs_pdbg_clk 2 CoreSight

The HPS-to-FPGA domain is used purely by the HPS-to-FPGA bridge. The FPGA drives the HPS-to-FPGA clock, which is asynchronous to all other clocks.

Table 61.   HPS-to-FPGA Domain
Clock Reset
h2f_axi_clock h2f_axi_reset

The Lightweight HPS-to-FPGA domain is used purely by the Lightweight HPS-to-FPGA bridge. The FPGA drives the Lightweight HPS-to-FPGA clock, which is asynchronous to all other clocks.

Table 62.  Lightweight HPS-to-FPGA Domain
Clock Reset
h2f_lw_axi_clock h2f_lw_axi_reset