H-Tile Hard IP Ethernet Intel® FPGA IP User Guide: Stratix® 10 Devices

ID 683430
Date 4/09/2024
Document Table of Contents

B.2.2. PHY Scratch Register

32 bits of scratch register space for testing.

Offset: 0x301

Access: RW

PHY Scratch Register Fields

Bit Name Description Access Reset
31:0 scratch   RW 0x0