H-Tile Hard IP Ethernet Intel® FPGA IP User Guide: Stratix® 10 Devices

ID 683430
Date 4/09/2024
Public
Document Table of Contents

B.2.5. TX PLL Locked

Offset: 0x320

TX PLL Locked Fields

Bit Name Description Access Reset
3:0 tx_pll_locked TX PLL Locked

1: TX PLL used by this physical lane is locked.

RO 0x0