H-Tile Hard IP Ethernet Intel® FPGA IP User Guide: Stratix® 10 Devices

ID 683430
Date 4/09/2024
Document Table of Contents

B.5.6. Enable Automatic TX Pause Retransmission

Offset: 0x607

Enable Automatic TX Pause Retransmission Fields

Bit Name Description Access Reset
8:0 en_holdoff Enable Holdoff timer.

Turns on automatic XOFF pause frame retransmission using a holdoff timer for the corresponding tx_pfc_pause port

Bits [7:0]: For PFC

Bit [8]: For PAUSE

1: Holdoff timer enabled.
  • EHIP transmits a new set of XOFF frames whenever the holdoff timer expires while a port or CSR request is still high for the corresponding queue
  • At power up this register defaults to 1
  • After i_csr_rst_n is asserted, this register value is set according to the module parameter flow_control_holdoff_mode
RW 0x1