H-tile Ethernet Hard IP User Guide: For Intel® Stratix® 10 Devices

ID 683430
Date 2/16/2022
Public
Document Table of Contents

B.6.68. TX Payload bytes with no errors (lower 32 bits)

TX Payload bytes with no errors
Records the number of TX payload bytes in a frame with no FCS, undersized, oversized, or payload length errors.
  • Packet bytes are all the bytes from an Ethernet packet except the preamble, the header, and the FCS; the count does include PAD bytes
  • When TX VLAN/SVLAN detection is enabled, VLAN/SVLAN header bytes are also removed from the count
  • Bytes from packets that are less than 72 bytes long are not counted (undersize)
  • When length checking is turned on, bytes from frames where the L/T field was a Length, and the length was greater than the number of bytes in the packet are not counted (length error)
  • Bytes from packets that are longer than Maximum TX Frame Size value are not counted (oversize)
  • Bytes from packets that were interrupted by any kind of control frame are not counted (error or malformed)
  • Bytes from packets with an FCS error are not counted (error)
  • Bytes from packets with an L/T field that is between 1501 and 1535 inclusive are not counted (illegal type/length field)
  • The total count is 64b, split into a lower and upper 32b chunk
  • Because the count can change while the register is being read, Intel recommends using snapshot or shadow to freeze the count before reading it.

Offset: 0x860

Access: RO

TX Payload bytes with no errors (lower 32 bits) Fields

Bit Name Description Access Reset
31:0 stats_pcnt16 Statistics word

4 bytes of an 8 byte EHIP Statistics

RO 0x0

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