1. About the H-tile Ethernet Hard IP Core
|Intel® Quartus® Prime Design Suite 21.1|
|IP Version 19.3.0|
Intel® Stratix® 10 H-tile FPGA production devices include a configurable, hardened protocol stack for Ethernet that is compatible with the IEEE 802.3 High Speed Ethernet Standard .
The H-Tile Hard IP for Ethernet Intel FPGA IP core supports 50 Gbps and 100 Gbps Ethernet data rate. The IP core is included in the Intel FPGA IP Library and is available from the Intel Quartus® Prime Pro Edition IP Catalog.
The IP core provides standard MAC and physical coding sublayer (PCS) functions with a variety of configuration and status registers.
The IP core is available with a 100GBASE-R4 Ethernet channel. You can choose a MAC+PCS, or a PCS Only, or an OTN, or a FlexE variation.
|IP Core Variation||Client Interface Type||Client Interface Width (Bits)|
|MAC+PCS||Avalon® Streaming Interface (Avalon-ST)||512|
|PCS Only||Media Independent Interface (MII)||256|
The 100GBASE-R4 Ethernet channel maps to four 25.78125 Gbps links. The FPGA serial transceivers are compliant with the IEEE 802.3-2015 High Speed Ethernet Standard CAUI-4 specification. The IP core configures the transceivers to implement the relevant specification for your IP core variation. You can connect the transceiver interfaces directly to an external physical medium dependent (PMD) optical module or to another device.