H-tile Ethernet Hard IP User Guide: For Intel® Stratix® 10 Devices

ID 683430
Date 2/16/2022
Public
Document Table of Contents

B.5.11. Set Uniform Holdoff

Set uniform holdoff

16b value specifying the minimum holdoff time for all PFC queues when Enable Uniform Holdoff register=1

Offset: 0x60C

Access: RW

Set Uniform Holdoff Fields

Bit Name Description Access Reset
15:0 holdoff_all_quanta Uniform holdoff time
16b minimum holdoff time required of all PFC queues when cfg_retransmit_holdoff_en.en_holdoff_all=1.
  • Times are programmed in holdoff quanta
    • For 100G links, 1 Holdoff Quanta = 2 clock cycles
  • Min value is 1, but to minimize wasted bandwidth, holdoff should be set as large as possible without exceeding the recommended max value
  • Max value for correct operation where holdoff retransmits PFC requests before the previously transmitted Quanta expires is:
    • For 100Gx4 links: min(Pause Quanta register value) - (50 + Maximum TX Frame Size register value/32)
  • At power up this register defaults to 0
  • After i_csr_rst_n is asserted, this register value is set according to the module parameter uniform_holdoff_quanta
RW 0x0

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