H-Tile Hard IP Ethernet Intel® FPGA IP User Guide: Stratix® 10 Devices

ID 683430
Date 4/09/2024
Public
Document Table of Contents

B.1.6. Auto Negotiation Config Register 3

Provides the following configuration options:
  • User base page low
  • Override AN_TECH [7:0]
  • Override AN_PAUSE

Offset: 0xC3

Access: RW

Auto Negotiation Config Register 3 Fields

Bit Name Description Access Reset
30:28 override_an_pause AN_PAUSE Override Value

When Override AN Parameters is enabled (override_an_parameters_enable=1), this register controls the value of AN_PAUSE used in the AN Base page

[0]: Pause Ability

[1]: Asymmetric Direction

[2]: Reserved

RW 0x0
23:16 override_an_tech AN_TECH Override Value, bits [7:0]

When Override AN Parameters is enabled (override_an_parameters_enable=1), this register controls the value of AN_TECH used in the AN Base page

[7]: 100GBASE-KR4

[8]: 100GBASE-CR4

RW 0x0
15:0 user_base_page_low User Controlled AN Base page (lower bits)

When User Controlled Base pages are turned on (an_base_pages_ctrl=1), this register provides the lower bits of the User base page that is used instead of the default page

[15]: Next page bit

[14]: ACK bit (controlled by State Machine)

[13]: Remote Fault bit [12:10]: Pause bits [9:5]: Echoed Nonce (set by SM) [4:0]: Selector

Note: Bit 49 (the PRBS bit of the AN BASE page) is generated by the SM.
RW 0x0