H-Tile Hard IP Ethernet Intel® FPGA IP User Guide: Stratix® 10 Devices

ID 683430
Date 4/09/2024

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Document Table of Contents

B.6.66. Configure TX Statistics Counters

Configure TX Statistics Counters

Configuration bits to control the behavior of the TX Statistics counters

Offset: 0x845

Configure TX Statistics Counters Fields

Bit Name Description Access Reset
2 tx_shadow_req TX Shadow Request
1: Freeze stats CSRs so that all TX Stats values read from the registers will be from the same moment.
  • Note that the actual stats collection counters are not frozen, but because they are all 'read' at the time of the freeze, they are cleared
  • If a shadow request is started while snapshot is active, a new capture will be executed
  • Likewise, if a shadow request is active while snapshot is asserted, a new capture will be executed
  • While either a shadow request or a capture is active, tx_shadow_on will be high
  • Snapshot and shadow requests apply to several of the RX PCS counters as well as MAC statistics
RW 0x0
1 rst_tx_parity Reset the TX Statistics Parity Error bit
1: Reset the parity error bit in cntr_TX_status
  • Parity error bit will remain in reset until rst_tx_parity is set back to 0
RW 0x0
0 rst_tx_stats Reset TX Statistics
1: Reset all TX Stats counters
  • TX stats will stay in reset until reset is set back to 0
  • Reset also applies when snapshot or shadow is active, and will clear the AVMM visible registers
  • rst_tx_stats does not clear the parity error bit
RW 0x0