H-Tile Hard IP Ethernet Intel® FPGA IP User Guide: Stratix® 10 Devices

ID 683430
Date 4/09/2024

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Document Table of Contents

B.2.6. RX CDR PLL Locked

Offset: 0x321

RX CDR PLL Locked Fields

Bit Name Description Access Reset
3:0 eio_freq_lock CDR PLL locked

1: Corresponding physical lane's CDR has locked to data for a 100G link.

RO 0x0