H-tile Ethernet Hard IP User Guide: For Intel® Stratix® 10 Devices

ID 683430
Date 2/16/2022
Document Table of Contents

6.9. Ethernet Reconfiguration Interface

You access Ethernet control and status registers of the H-tile Ethernet Hard IP core during normal operation using an Avalon® -MM interface called the Ethernet reconfiguration interface. The interface responds regardless of the link status. It also responds when the IP core is in a reset state driven by any reset signal or soft reset other than the i_csr_rst_n and soft_sys_rst signals. Asserting the i_csr_rst_n signal resets all Ethernet control and status registers, including the statistics counters; while this reset is in process, the Ethernet reconfiguration interface does not respond.
Table 22.  Ethernet Reconfiguration Interface The signals in this interface are clocked by the i_reconfig_clk clock and reset by the i_reconfig_reset signal. This clock and reset control this interface and the transceiver reconfiguration interface. However, the two interfaces access disjoint sets of registers.
Signal Description

Drives the Avalon® -MM register address.


When asserted, specifies a read request.

i_eth_reconfig_write When asserted, specifies a write request.
o_eth_reconfig_readdata[31:0] Drives read data. Valid when o_eth_reconfig_readdata_valid is asserted.
o_eth_reconfig_readdata_valid When asserted, indicates that i_eth_reconfig_read_data[31:0] is valid.
i_eth_reconfig_writedata[31:0] Drives the write data.
o_eth_reconfig_waitrequest Indicates that the Ethernet reconfiguration interface is not ready to complete the read or write transaction.

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