H-Tile Hard IP Ethernet Intel® FPGA IP User Guide: Stratix® 10 Devices

ID 683430
Date 4/09/2024

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Document Table of Contents

B.3.9. TX MAC Source Address Lower Bytes

Offset: 0x40C

TX MAC Source Address Lower Bytes Fields

Bit Name Description Access Reset
31:0 saddrl Source Address Insertion Source Address lower bytes
Lower 4 bytes of the 6 byte source address that is inserted by the TX MAC when TX source address insertion is enabled
  • At power-on, saddrl is set to 1
  • After i_csr_rst_n is asserted, saddrl is set to the value given by module parameter txmac_saddr[31:0]
RW 0x22334455