H-tile Ethernet Hard IP User Guide: For Intel® Stratix® 10 Devices

ID 683430
Date 2/16/2022
Public
Document Table of Contents

1.1. IP Core Supported Features

The IP core is designed to the IEEE 802.3-2015 High Speed Ethernet Standard available on the IEEE website (www.ieee.org). The MAC provides cut-through frame processing to optimize latency, and supports full wire line speed with a 64-byte frame length and back-to-back or mixed length traffic with no dropped packets. All H-tile Ethernet Hard IP core variations are in full-duplex mode. These IP core variations offer the following features:

Table 2.   H-tile Ethernet Hard IP Features
Features Description
PCS Hard IP logic that interfaces seamlessly to Intel® Stratix® 10 FPGA 25.78125 Gbps serial transceivers.
CAUI-4 external interface consisting of four FPGA hard serial transceiver lanes operating at 25.78125 Gbps.
Supports CAUI-4 links based on 64B/66B encoding with data striping and alignment markers to align data from multiple lanes.
Supports Auto-negotiation (AN) as defined in IEEE Standard 802.3-2015 Clause 73 .
Support link training (LT) as defined in IEEE Standard 802.3-2015 Clauses 92 and 93 .
RX Skew Variation tolerance that exceeds the IEEE 802.3-2015 High Speed Ethernet Standard Clause 80.5 requirements.
Optical Transport Network (OTN) Optional 100GE constant bit rate (CBR), with TX and RX PCS66 bit encoding and scrambling disabled.
Note: The H-tile Ethernet Hard IP provides preliminary support for the OTN feature. For further inquiries, contact your nearest Intel sales representative or file an Intel Premier Support (IPS) case on https://www.intel.com/content/www/us/en/programmable/my-intel/mal-home.html.
Flexible Ethernet (FlexE) Optional 100GE constant bit rate (CBR) with TX and RX PCS66 scrambler/descrambler.
Frame Structure Control Support for jumbo packets.
RX CRC pass-through control.
1000 bits RX PCS lane skew tolerance for 100G links, which exceeds the IEEE 802.3-2015 High Speed Ethernet Standard Clause 82.2.12 requirements.
Optional per-packet TX CRC generation and insertion.
RX and TX preamble pass-through options for applications that require proprietary user management information transfer.
Optional TX MAC source address insertion.
TX automatic frame padding to meet the 64-byte minimum Ethernet frame length on the Ethernet link. Optional per-packet disabling of this feature.
TX error insertion capability supports client invalidation of in-progress input to TX client interface.
Optional Deficit Idle Counter (DIC) options to maintain a finely controlled 8-byte, 10-byte, or 12-byte inter-packet gap (IPG) minimum average, or allow the user to drive the IPG from the client interface.
Frame Monitoring and Statistics RX cyclic redundancy check (CRC) checking and error reporting.
Optional RX strict Start Frame Delimiter (SFD) checking per IEEE specification.
Optional RX strict preamble checking per IEEE specification.
RX malformed packet checking per IEEE specification.
Received control frame type indication.
Statistics counters.
Snapshot feature for precisely timed capture of statistics counter values.
Optional fault signaling: detects and reports local fault and generates remote fault, with support for unidirectional link fault as defined in IEEE 802.3-2015 High Speed Ethernet Standard Clause 66.
Flow Control Optional IEEE 802.3-2015 Ethernet Standard Clause 31 Ethernet flow control operation using the pause registers or pause interface.
Optional priority-based flow control that complies with the IEEE Standard 802.1Q-2014—Amendment 17: Priority-based Flow Control.
Pause frame filtering control.
Software can dynamically toggle local TX MAC data flow to support selective input flow cut-off.
Debug and testability Optional serial PMA loopback (TX to RX) at the serial transceiver for self-diagnostic testing.
Optional parallel loopback (TX to RX) at the MAC or at the PCS for self-diagnostic testing.
Bit-interleaved parity error counters to monitor bit errors per PCS lane.
RX PCS error block counters to monitor errors during and between frames.
Malformed and dropped packet counters.
High BER detection to monitor link bit error rates over all PCS lanes.
Optional scrambled Idle test pattern generation and checking.
Snapshot feature for precisely timed capture of statistics counter values.
TX error insertion capability supports test and debug.
Optional access to Native PHY Debug Master Endpoint (NPDME) for debugging or monitoring PHY signal integrity.
User System Interface Avalon Memory-Mapped (Avalon-MM) management interface to access the IP core control and status registers.
Avalon-ST data path interface connects the MAC to client logic with the start of frame in the most significant byte (MSB) in MAC+PCS variations. Interface for 100GBASE-R4 variations has 512 bits, to ensure the data rate despite this RX client interface SOP alignment and RX and TX preamble passthrough option.
MII data path interface connects the PCS to client logic in PCS Only variations. Interface for 100GBASE-R4 variations has 256 bits.
Hardware and software reset control.
Supports Synchronous Ethernet (SyncE) by providing a CDR recovered clock output signal to the device fabric.

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