H-Tile Hard IP Ethernet Intel® FPGA IP User Guide: Stratix® 10 Devices

ID 683430
Date 4/09/2024
Public
Document Table of Contents

B.5.36. Enable RX Pause Frame Processing

Offset: 0x705

Enable RX Pause Frame Processing Fields

Bit Name Description Access Reset
7:0 en_rx_pause Enable Rx Pause
1:Enable PFC port for selected queue
  • After power-on, this reset is set to 0
  • After i_csr_rst_n, this register is set to a value given by the module parameter flow_control
RW 0x1