H-Tile Hard IP Ethernet Intel® FPGA IP User Guide: Stratix® 10 Devices

ID 683430
Date 4/09/2024

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6.5. FlexE and OTN Mode TX Interface

The H-Tile Hard IP for Ethernet IP core TX client interface in FlexE and OTN variations employs the PCS66 interface protocol.

The FlexE and OTN variations allow the application to write 66b blocks to the TX PCS, bypassing the TX MAC.

  • In FlexE mode, the TX encoder in the PCS is also bypassed.
  • In OTN mode, both the TX encoder and the scrambler are bypassed.

The client acts as a source and the TX PCS acts as a sink in the transmit direction.

Note: The H-Tile Hard IP for Ethernet IP provides preliminary support for the OTN feature. For further inquiries, contact your nearest Intel sales representative or file an Intel Premier Support (IPS) case and quote ID #22019851155.
Table 18.  Signals of the PCS66 TX Interface

Signal Name



TX PCS 66b data for 4 blocks.

  • In FlexE mode, the data presented is scrambled and bit-interleaved for 100GBASE-R4 transmission.
  • In OTN mode, the data is only bit-interleaved and unscrambled.


When asserted, indicates that the TX PCS 66b data is valid.

Must be asserted when the TX PCS 66b ready signal is asserted.


TX PCS 66b ready signal.

When asserted, indicates the PCS is ready to receive new data.


Alignment marker insertion bit.

In FlexE mode, asserting this signal causes the PCS to allow gaps for the alignment markers in place of the data presented on the TX PCS data signal. The application marks the block as an alignment marker and the scrambler does not process the data.

In OTN mode, this signal is not used. The input stream is expected to include its alignment markers.

Figure 28. Transmitting Data Using the PCS66 TX InterfaceThe figure shows how to write the 66b blocks directly to the TX PCS in FlexE and OTN mode using the PCS66 TX Interface.
Figure 29. Alignment Marker Insertion on the TX PCS66 Interface