6.7. Ethernet Link and Transceiver Signals

H-Tile Hard IP Ethernet Intel® FPGA IP User Guide: Stratix® 10 Devices

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Date 4/09/2024

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6.7. Ethernet Link and Transceiver Signals

The H-tile HIP for Ethernet includes transceivers that implement four physical lanes at 25.78125 MHz and require two separately instantiated advanced transmit (ATX) PLLs to generate the high speed serial clocks. On Stratix 10 devices, only the ATX PLL supports the required data rate.

Table 20. Transceiver Signals
Signal	Description
`o_tx_serial[3:0]`	TX transceiver data. Each `o_tx_serial` bit becomes two physical pins that form a differential pair.
`i_rx_serial[3:0]`	RX transceiver data. Each `i_rx_serial` bit becomes two physical pins that form a differential pair.
`i_clk_ref`	The input clock `i_clk_ref` is the reference clock for the high-speed serial clocks and the datapath parallel clocks. This clock must have a frequency of 322.265625 MHz or 644.53125 MHz with a ±100 ppm accuracy per the IEEE 802.3-2015 Ethernet Standard. In addition, `i_clk_ref` must meet the jitter specification of the IEEE 802.3-2015 Ethernet Standard. The PLL and clock generation logic use this reference clock to derive the transceiver and PCS clocks. The input clock should be a high quality signal on the appropriate dedicated clock pin. Refer to the Stratix® 10 Device Datasheet for transceiver reference clock phase noise specifications.
`i_tx_serial_clk[1:0]`	High speed serial clocks driven by the ATX PLLs. IP core have two serial clocks, each driven from a separate ATX PLL. The frequency of these clocks is 12.890625 GHz. You must drive these clocks from ATX PLLs that you configure separately from the H-Tile Hard IP for Ethernet IP core. Refer to Adding the Transceiver PLLs.
`i_tx_pll_locked[1:0]`	Lock signals from the ATX PLLs. Each bit indicates the corresponding ATX PLL is locked. IP core have two PLL locked signals, each driven from a separate ATX PLL. You must drive these clocks from ATX PLLs that you configure separately from the H-Tile Hard IP for Ethernet IP core. Refer to Adding the Transceiver PLLs. The `o_clk_pll_div64` and `o_clk_pll_div66` clocks are reliable only after the `i_tx_pll_locked` bits are all high.

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H-Tile Hard IP Ethernet Intel® FPGA IP User Guide: Stratix® 10 Devices

6.7. Ethernet Link and Transceiver Signals