H-Tile Ethernet Hard IP User Guide: For Intel® Stratix® 10 Devices

ID 683430
Date 1/18/2024
Public
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B.3.8. EHIP TX MAC Feature Configuration

EHIP TX MAC Feature Configuration

Register for configuring EHIP specific TX MAC features

Offset: 0x40B

Access: RW

EHIP TX MAC Feature Configuration Fields

Bit Name Description Access Reset
31:15 am_period TX Alignment Marker Period
Sets the number of TX clock cycles that are used to send regular data between Alignment Markers
  • At power-on, this is set to 17'd81915
  • After i_csr_rst_n, if the module parameter sim_mode is enabled, this parameter is set to a simulation mode value appropriate for the selected rate
  • After i_csr_rst_n, if the module parameter sim_mode is disabled, this parameter is set to mission mode value appropriate for the selected rate
RW 0x13FFB
9 txcrc_covers_preamble Enable CRC over preamble

0: TX CRC calculated over Ethernet Frame (default)

1: TX CRC calculated over frame plus preamble
  • At power-on, txcrc_covers_preamble is set to 0
  • After i_csr_rst_n is asserted, txcrc_covers_preamble is set to the value given by module parameter txcrc_covers_preamble
RW 0x0
5:3 am_width Sets the number of cycles for each AM pulse
Sets the number of TX clock cycle that the AM pulse is held high
  • After power-up, am_width is set to 5
  • After i_csr_rst_n is asserted, am_width is set according to the rate of the channel
  • Set to 5 for 100G channels
RW 0x5
2:1 ipg DIC Average Min IPG
Sets the average minimum IPG enforced by the Deficit Idle Counter:
  • 2'd0: 12 bytes (default)
  • 2'd1:10 bytes
  • 2'd2:8 bytes
  • 2'd3:1 byte
  • After power-up, ipg is set to 0 (12 bytes)
  • After i_csr_rst_n is asserted, ipg is set to the value given by the module parameter tx_ipg_size
RW 0x0
0 en_pp Enable TX Preamble Passthrough

1: Preamble-passthrough mode enabled - bytes 1 to 7 of each SOP word will be used as preamble bytes at the start of the Ethernet packet

0: A standard Ethernet preamble will be used for TX packets

RW 0x0