H-Tile Hard IP Ethernet Intel® FPGA IP User Guide: Stratix® 10 Devices

ID 683430
Date 4/09/2024

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B. Ethernet Reconfiguration and Status Register Descriptions

You access the Ethernet registers for the H-Tile Hard IP for Ethernet IP using the Avalon-MM Ethernet reconfiguration interface on each channel. These registers use 32-bit addresses; they are not byte addressable.

Write operations to a read-only register field have no effect. Read operations that address a Reserved register return an unspecified result. Write operations to Reserved registers have no effect. Accesses to registers that do not exist in your IP core variation, or to register bits that are not defined in your IP core variation, have an unspecified result. You should consider these registers and register bits Reserved. Although you can only access registers in 32-bit read and write operations, you should not attempt to write or ascribe meaning to values in undefined register bits.

Table 28.  Register Base Addresses
Word Offset Register Type
0xB0-0x0E8 Auto Negotiation and Link Training registers
0x300-0x3FF PHY registers
0x400-0x4FF TX MAC registers
0x500-0x5FF RX MAC registers
0x600-0x7FF Pause and Priority- Based Flow Control registers
0x800-0x8FF TX Statistics Counter registers
0x900-0x9FF RX Statistics Counter registers
Note: Do not attempt to access any register address that is Reserved or undefined. Accesses to registers that do not exist in your IP core variation have unspecified results.