H-Tile Hard IP Ethernet Intel® FPGA IP User Guide: Stratix® 10 Devices

ID 683430
Date 4/09/2024
Public
Document Table of Contents

2.5. IP Core Testbenches

Intel provides a design example and a testbench that you can generate for the H-Tile Hard IP for Ethernet IP core.

To generate the testbench, in the H-Tile Hard IP for Ethernet parameter editor, you must first set the parameter values for the IP core variation you intend to generate in your end product. If you do not set the parameter values for your DUT to match the parameter values in your end product, the testbench you generate does not exercise the IP core variation you intend.

The testbench demonstrates a basic test of the IP core. It is not intended to be a substitute for a full verification environment.