H-Tile Hard IP Ethernet Intel® FPGA IP User Guide: Stratix® 10 Devices

ID 683430
Date 4/09/2024

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Document Table of Contents

B.2.12. PCS Error Injection

Offset: 0x327

PCS Error Injection Fields

Bit Name Description Access Reset
19:0 inj_err Inject Error

0->1: Flip bits to inject encoding errors in corresponding virtual lane

0 :Clear all error injection settings

  • For EHIP with rate set to 100G, bits 0 to 19 are valid, and correspond to virtual lanes 0...19
RW 0x0