H-tile Ethernet Hard IP User Guide: For Intel® Stratix® 10 Devices

ID 683430
Date 2/16/2022
Public
Document Table of Contents

2.4.2. Pin Assignments

When you integrate your H-tile Ethernet Hard IP core instance into your design, you must make appropriate pin assignments. You can create a virtual pin to avoid making specific pin assignments for top-level signals until you are ready to map the design to hardware.

Intel® Stratix® 10 H-tile devices offer a single hard IP for Ethernet block on each H-tile. Your design must not include pin assignments that conflict with its location. In devices with multiple H-tiles, you can specify the H-tile to which the Ethernet link serial pins should map. Refer to 100G Configuration in the Ethernet Hard IP section of the Intel® Stratix® 10 L- and H-Tile Transceiver PHY User Guide or the figures in Channel Placement.

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