2.4.5. Placement Settings for the H-tile Ethernet Hard IP Core
The Intel® Quartus® Prime Pro Edition software provides the options to specify design partitions and Logic Lock (Standard) Plus regions for block-based design, to control placement on the device. To achieve timing closure for your design, you might need to provide floorplan guidelines using one or both of these features.
In all cases you must take into account the location of the hard IP for Ethernet on the target H-tile(s). Each H-tile offers a single hard IP for Ethernet block. Refer to the Ethernet Hard IP section of the Intel® Stratix® 10 L- and H-Tile Transceiver PHY User Guide or the figures in Channel Placement.
The appropriate floorplan is always design-specific and depends on your full design.
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