H-Tile Ethernet Hard IP User Guide: For Intel® Stratix® 10 Devices

ID 683430
Date 1/18/2024
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6.11. Reset Signals

The IP core has three external hard reset inputs. These resets are asynchronous and are internally synchronized. In addition, the IP core supports a dedicated reset signal that resets the transceiver and Ethernet reconfiguration interfaces but not the transceiver and Ethernet reconfiguration registers.

Assert the asynchronous resets for ten i_reconfig_clk cycles or until you observe the effect of their specific reset. Asserting the external hard reset i_csr_rst_n returns all Ethernet reconfiguration registers to their original values. o_rx_pcs_ready and o_tx_lanes_stable are asserted when the core has exited reset successfully.
Table 24.   Reset Signals

Signal

Description

i_tx_rst_n Active-low hard-reset asynchronous signal. Resets the TX interface, including the TX PCS and TX MAC. This reset leads to the deassertion of the o_tx_lanes_stable output signal.
i_rx_rst_n

Active-low hard-reset asynchronous signal. Resets the RX interface, including the RX PCS and RX MAC. This reset leads to the deassertion of the o_rx_pcs_ready output signal.

i_csr_rst_n

Active-low hard asynchronous global reset. Resets the full IP core. Resets the TX MAC, RX MAC, TX PCS, RX PCS, transceivers (transceiver reconfiguration registers and interface), and Ethernet reconfiguration registers. This reset leads to the deassertion of the o_tx_lanes_stable and o_rx_pcs_ready output signals.

i_reconfig_reset Resets the H-tile Ethernet Hard IP core Avalon® -MM interfaces, both the transceiver reconfiguration interface and the Ethernet reconfiguration interface, but not the registers to which they provide access.

This signal is synchronous with the i_reconfig_clk clock.