H-Tile Hard IP Ethernet Intel® FPGA IP User Guide: Stratix® 10 Devices

ID 683430
Date 4/09/2024

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Document Table of Contents

B.2.14. BER Count

Offset: 0x32A

ber_count Fields

Bit Name Description Access Reset
31:0 count BER Count
  • 32b count that increments each time when it detects invalid sync header
  • Rolls over when maximum count is reached
  • Clears when the channel is reset
  • Can be captured using snapshot or RX shadow request
RO 0x0