H-tile Ethernet Hard IP User Guide: For Intel® Stratix® 10 Devices

ID 683430
Date 9/06/2023
Document Table of Contents Clock Connection Requirements

Make the following clock connections:

  • The same clock should drive the i_clk_ref input signal to the IP core and the reference clocks of the ATX PLLs to which it is connected. If your design cannot drive i_clk_ref with the same clock as the PLL reference clocks, you must ensure the two clocks have the same nominal rate.
  • The output clock o_clk_pll_div64 drives both the i_clk_rx and the i_clk_tx input clocks.
  • In case of multiple instances of the IP core, if the same clock drives the i_clk_ref input clock of all the instances and all of their ATX PLLs, the o_clk_pll_div64 output clock from one instance can drive all instances of i_clk_rx and i_clk_tx.

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