H-Tile Hard IP Ethernet Intel® FPGA IP User Guide: Stratix® 10 Devices

ID 683430
Date 4/09/2024

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Document Table of Contents

B.2.3. PHY Configuration

Offset: 0x310

PHY Configuration Fields

Bit Name Description Access Reset
5 set_data_lock Set data lock

1: Force PLL to lock to data

RW 0x0
4 set_ref_lock Set ref lock

1: Force PLL to lock to reference

RW 0x0
2 soft_rx_rst Soft RXP Reset

1: Resets the RX PCS and RX MAC.

RW 0x0
1 soft_tx_rst Soft TXP Reset

1: Resets the TX PCS and TX MAC.

RW 0x0
0 eio_sys_rst Ethernet IO System Reset

1: Resets the IP core (TX and RX MACs, Ethernet reconfiguration registers, PCS, and transceivers).

RW 0x0